{City}, {State/Province} — January 6, 2026 — Leads & Copy —
Cadence (Nasdaq: CDNS) has announced a Chiplet Spec-to-Packaged Parts ecosystem designed to streamline engineering and speed up the market launch of chiplets for physical AI, data centers, and high-performance computing (HPC) applications.
The company’s initial IP partners include Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, along with silicon analytics partner proteanTecs. Cadence is working with Samsung Foundry to create a silicon prototype demonstration of the Cadence® Physical AI chiplet platform, featuring pre-integrated partner IP on the Samsung Foundry SF5A process, to lower risk and facilitate customer adoption.
Cadence and Arm are extending their collaboration to boost innovation in physical and infrastructure AI applications. Cadence will use the Arm® Zena™ Compute Subsystem (CSS) and other IP to improve Cadence’s Physical AI chiplet platform and Chiplet Framework. These new Cadence solutions will support the edge AI processing requirements for automobiles, robotics, and drones, as well as the needs of standards-based I/O and memory chiplets for data center, cloud, and HPC applications. These alliances aim to simplify engineering, provide a low-risk path to chiplet adoption, and promote smarter, safer, and more efficient systems.
According to David Glasco, vice president of the Compute Solutions Group at Cadence, multi-die and chiplet-based architectures are crucial for achieving greater performance and cost efficiency. Cadence’s chiplet solutions are designed to optimize costs, provide customization flexibility, and enable configurability. By integrating its IP and SoC design expertise with pre-integrated and pre-validated IP from its partner ecosystem, Cadence aims to accelerate the development of chiplet-based solutions and help customers mitigate risk.
Cadence has developed spec-driven automation to generate chiplet framework architectures that combine Cadence IP and third-party partner IP with chiplet management, security, and safety features, all supported by advanced software. The generated EDA tool flow enables simulation with the Cadence Xcelium™ Logic Simulator and emulation with the Cadence Palladium® Z3 Enterprise Emulation Platform, while the physical design flow employs real-time feedback for efficient place-and-route cycles. The resulting chiplet architectures comply with standards to ensure interoperability across the chiplet ecosystem, including adherence to the Arm Chiplet System Architecture and future OCP Foundational Chiplet System Architecture. Cadence’s Universal Chiplet Interconnect Express™ (UCIe™) IP provides die-to-die connectivity, while a protocol IP portfolio enables integration of interfaces such as LPDDR6/5X, DDR5-MRDIMM, PCI Express® (PCIe®) 7.0, and HBM4.
A prototype of the Cadence base system chiplet, part of the Cadence Physical AI chiplet platform, has already been validated. It incorporates the Cadence chiplet framework, UCIe 32G, and LPDDR5X IP.
Supporting Partner Quotes:
Suraj Gajendra, Vice President of Products and Solutions, Physical AI Business Unit, Arm, said that by leveraging Arm Zena CSS, Cadence’s chiplet platform will meet the requirements of next-generation intelligent systems that will advance the physical AI landscape, accelerate chiplet adoption, and help customers reduce design complexity.
Guillaume Boillet, Vice President of Strategic Marketing, Arteris, said that together with Cadence, they are enabling customers to confidently adopt chiplet architectures with high-bandwidth, scalable, and production-proven interconnect technology for next-generation multi-die systems.
Charles Hsu, Chairman, eMemory, said that the combination of eMemory technology and Cadence’s security subsystem results in a Physical AI Chiplet platform delivering secure storage and long-lifecycle key management, reinforcing the strong hardware foundation provided by Cadence for die-to-die security and safety in advanced chiplet designs.
Scott Chang, CEO, M31 Technology, said that M31 delivers world-class MIPI PHY interface IP that enables customers to rapidly realize advanced chiplet solutions with flexible MIPI CSI and DSI integration.
Ziv Paz, VP of Business Development, proteanTecs, said that the collaboration is delivering real value for customers building advanced SoCs and systems for automotive and autonomous applications.
Taejoong Song, Vice President of Foundry Technology Planning, Samsung Electronics, said that through this trusted partnership, they look forward to the successful expansion of the Chiplet Spec-to-Packaged Parts ecosystem and helping customers accelerate reliable paths to cutting-edge silicon solutions for physical AI applications, including next-generation automotive designs.
Pawel Banachowicz, PLL Product Line Development Director, Silicon Creations, said that they are excited to extend their collaboration to help accelerate next-generation chiplet-based designs.
Carl Ruggiero, CEO, Trilinear Technologies, said that collaborating with Cadence enables them to drive high-performance video connectivity and deliver flexible, future-ready display solutions for the chiplet ecosystem.
Related Resources mentioned are an eBook: Helping You Realize Your Chiplet Ambitions; Blogs: From Spec to Silicon: Successful Physical AI System Chiplet Bring-Up, Cadence Transforms Chiplet Technology with First Arm-Based System Chiplet, and Jumpstarting the Automotive Chiplet Ecosystem; and a Webinar: Chiplets Solutions: Helping You Realize Your Chiplet Ambitions.
Cadence is a market leader in AI and digital twins. Cadence solutions offer opportunities at www.cadence.com.
Source: Cadence
